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具体招聘信息：标 题: Cadence ICD PV intern wanted发信站: 饮水思源 (2007年11月29日23:35:52 星期四)location: Software Park, Zhangjiang, Shanghai requirements:-The candidate should have basic knowledge of HDL(Verilog preferred) and microelectronics. Script skill such as Cshell, tcl, perl is preferable.-Knowledge of Digital backend flow is highly preferable. Previous experience of ASIC design (Cadence/Synopsys/Magma platforms) is highly preferable. -Good English communication skills. -Major in EE/CS/Metech, postgraduate of Grade 2responsibilities: -validate EDA software in ASIC design flow. -responsible for developing, applying, and maintaining quality standards for complex EDA software system. any one interested in the position can send your resume to jzwang@cadence.com with subject "apply for Cadence ICD PV intern -- your name"--中的精神
※ 来源:·饮水思源 bbs.sjtu.edu.cn·[FROM: 60.63.210.121]
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